Voyager FDS Emulator | Flight Data Subsystem

◈ FDS Assembly

◈ Registers

RA (Accumulator)

0000

RB (Auxiliary)

0000

PC (Program Counter)

000

Cycles

ZERO

OVFL

CARRY

BANK

◈ Memory

000: 0000 0000 0000 0000

◈ Output

◈ DMA Channels

MDS

DSS

ISS

PRA

◈ Instructions

MLD Load mem→RA

MRD Store RA→mem

ADD RA + mem

SUB RA - mem

AND RA & mem

JMP Jump

SKZ Skip if zero

SKP Skip if +

WAT Halt

DW Define word

◈ Architecture

Clock

806.4 kHz

~400,000 instructions/sec

Cycle Time

2.48 µs

Glacial by modern standards

Memory

8K × 16-bit

CMOS RAM, two 4K banks

Registers

RA, RB + 128

Working + special registers

Serial I/O

32 in / 16 out

For all those instruments

DMA

4 channels

MDS, DSS, ISS, PRA @ 115.2 kbps

Interrupt

2.5 ms

Periodic error recovery

Word Size

16-bit

12-bit addresses, 4-bit opcode

Original Documentation
The docs folder contains scanned JPL documentation from 1974-1977, preserved by Wichita State University Special Collections.